System software "watchdog" design ideas:
1. Setting of watchdog timer T0. Set the working mode of T0 in the initialization block and enable the interrupt and count function. The system Fosc=12 MHz, T0 is a 16-bit counter, the maximum count value is (2 to the 16th power)-1=65 535, the T0 input count frequency is .Fosc/12, and the overflow period is (65 535+1)/1 =65 536 (μs).
2. Calculate the time taken by the master program to cycle once. Considering the function modules of the system and the number of cycles, the running time of the main control program of this system is about 16.6 ms. The system sets the "Watchdog" timer T0 to 30 ms (the initial value of T0 is 65 536-30 000 = 35 536). The initial value of T0 will be refreshed every cycle of the master program. If the program enters an "infinite loop" and the initial value of T0 is not refreshed within 30 ms, then the "watchdog" timer T0 will overflow and request an interrupt.
3. Design the interrupt service program corresponding to T0 overflow. This subroutine only needs one instruction, that is, write the "unconditional transfer" command at the interrupt vector address (000BH) corresponding to T0, drag the computer back to the first line of the whole program, re-initialize the MCU and get the correct execution order.
Fundamental
The watchdog, also known as the watchdog timer, is a timer circuit. It usually has an input, called the dog or service the dog, and an output to the RST end of the MCU. When the MCU is working normally, every other segment. Time to output a signal to the feeding dog, clear the WDT. If the dog is not fed for more than the specified time (usually when the program runs away), the WDT timing will be exceeded, a reset signal will be given to the MCU to reset the MCU. Prevent the MCU from crashing. The role of the watchdog is to prevent the program from running away. It also prevents an infinite loop from occurring when the program is running online.
Working principle: After the system is running, the watchdog counter is started, and the watchdog starts to count automatically. If the watchdog is not cleared after a certain period of time, the watchdog counter will overflow and cause the gatekeeper. The dog is interrupted, causing a system reset. Therefore, pay attention to clearing the watchdog when using a chip with a watchdog.
Hardware watchdog
The hardware watchdog uses a timer to monitor the running of the main program. That is to say, during the running of the main program, we need to reset the timer before the timing time expires. If an infinite loop occurs, or the PC pointer Can't come back. Then, after the timing time is up, the MCU will be reset. Commonly used WDT chips such as MAX813, 5045, IMP 813, etc., the price ranged from 4 to 10 yuan.
Software watchdog
The principle of software watchdog technology is similar to this, except that it is implemented by software. We still use the 51 series. We know that there are two timers in the 51 MCU, we can use these two timers. Monitor the operation of the main program. We can set a certain timing time for T0. When a timer interrupt is generated, a variable is assigned. This variable has an initial value at the beginning of the main program operation. Here we have to set the timing value to be smaller than The running time of the main program, so that the value of the variable is judged at the end of the main program. If the value changes as expected, it indicates that the T0 interrupt is normal, and if there is no change, the program is reset. For T1, we use to monitor the running of the main program. We set a certain timing time for T1 and reset it in the main program. If it cannot be reset within a certain time, the timer interrupt of T1 will make the MCU. Reset. Here, the timing time of T1 should be set larger than the running time of the main program, leaving a certain margin for the main program. The interruption of T1 is normal or not, and we are monitored by the T0 timer interrupt subroutine. This is enough to become a loop, T0 monitors T1, T1 monitors the main program, and the main program monitors T0 again to ensure stable operation of the system.
Watchdog use note
Most 51 series MCUs have a watchdog that will cause a reset when the watchdog is not cleared by timing. This prevents the program from running away. It also prevents an infinite loop from occurring when the program is running online. The designer must be aware of the watchdog's overflow time to decide to clear the watchdog when appropriate. Clear watchdogs should not be too frequent or waste resources. When the program is running normally, the software sets the number of timers at regular intervals (less than the overflow period of the timer) to prevent false reset caused by overflow interrupts.
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