CortexM3 is ARM's first ARMv7M-based microcontroller core, which is quite different from ARM7 in terms of instruction execution, exception control, clock management, trace debugging and memory protection. Especially in the exception processing mechanism has been greatly improved, its abnormal response only takes 12 clock cycles. NVIC (Nested Vectored Interrupt Controller) is a tightly coupled component of the CortexM3 processor that can be configured with 1 to 240 physical interrupts with 256 priority levels and 8 levels of preemption priority. Excellent exception handling capability [1]. At the same time, the use of pre-empTIon, tail-chaining, and late-arriving techniques greatly reduces the response time of anomalous events.
An exception or interrupt is a mechanism by which the processor responds to an unexpected event in the system. When an exception occurs, the CortexM3 automatically pushes the program counter (PC), program status register (xPSR), link register (LR), and R0~R3, R12 registers into the stack via hardware. While the Dbus (data bus) saves the processor state, the processor identifies the exception vector from a relocatable vector table via Ibus (instruction bus) and obtains the address of the ISR function, ie, protects the scene and fetches the exception vector. It is processed in parallel. Once the push and fetch instructions are completed, the interrupt service routine or fault handler begins execution. After the ISR is executed, the hardware performs a pop operation, and the program before the interrupt resumes normal execution. Figure 1 shows the exception handling flow of the CortexM3 processor [2].
1 CortexM3 exception type
Compared with ARM7, CortexM3 has a big difference in the classification and priority of anomalies, as listed in Table 1.
CortexM3 divides exceptions into reset, non-maskable interrupts, hard faults, memory management, bus faults and application faults, SVcall, debug monitor exceptions, PendSV, SysTIck, and external interrupts. CortexM3 uses a vector table to determine the entry address of the exception. Unlike most other ARM cores, the CortexM3 vector table contains the address of the exception handler and ISR, not the instruction. The initial stack pointer and address of the reset handler must be at 0x0 and 0x4, respectively. These values ​​are loaded into the appropriate CPU registers in subsequent resets. The vector table offset control register positions the vector table in CODE (Flash) or SRAM. At reset, it is CODE mode by default, but can be repositioned. After the exception is accepted, the processor obtains the address through the Ibus lookup table and executes the exception handler.
In the priority allocation of CortexM3, the lower priority value has a higher priority. The NVIC divides the priority of the exception into two parts: the pre-empTIon priority part and the sub-priority part. The interrupt application/reset control register can be used to determine the proportion of the two parts. The preemption priority and sub-priority work together to determine the priority of the exception. The preemption priority is used to determine whether preemption occurs. An exception can only occur when the preemption priority is higher than the preemption priority of another exception. When multiple pending exceptions have the same preemption priority, the subpriority acts [3]. The priority permissions set by the NVIC are higher than the hardware default priority. When there are multiple exceptions with the same priority, the size of the exception number is compared, and the exception number is activated preferentially.
2 CortexM3 exception handling
2.1 Abnormal entry
When an exception occurs, the CortexM3 processor saves the processor state through Dbus by hardware, and simultaneously reads the SP in the vector table through Ibus, updates the PC and LR, and executes the interrupt service routine.
To cope with higher priority anomalies after the stack operation phase, CortexM3 supports late and preemptive mechanisms to respond deterministically to a variety of possible events. Preemption is a response mechanism to higher priority exceptions. The CortexM3 exception preemption process [2] is shown in Figure 2. When a new higher priority exception arrives, the processor interrupts the current process and performs a higher priority exception operation, which causes an exception nesting. Being late is a mechanism used by the processor to speed up preemption. If an exception with a higher priority arrives during the last exception execution push, the processor saves the state operation continues because the saved state is the same for both exceptions. However, the NVIC immediately gets a higher priority exception vector address. This starts the ISR of the high priority exception after the processor state is saved.
2.2 Abnormal return
The operation of the CortexM3 exception return is shown in Figure 3. When returning from an exception, the processor may be in one of the following situations:
â—† The tail chain to a suspended exception that has a higher priority than all exceptions in the stack;
â—† If there is no pending exception, or if the highest priority exception in the stack has a higher priority than the pending highest priority exception, then return to the most recent pushed ISR;
â—† If no exception has been suspended or is on the stack, return to Tread mode.
In response to new higher priority exceptions that may be encountered during the exception return phase, CortexM3 supports a completely hardware-based tailchain mechanism that simplifies the movement between active and pending exceptions, with no redundancy between the two exceptions. Back to back processing is implemented in the case of state save and resume instructions. Two conditions that occur in the tail chain: a new exception is generated when the exception returns; the priority of the suspended exception is higher than the priority of all pushed exceptions.
After the tail chain occurs, the CortexM3 process is shown in the tail chain branch in Figure 3. At this point, the CortexM3 processor terminates the ongoing pop operation and skips the push operation on the new exception entry, while immediately withdrawing the vector of the pending exception via Ibus. After the ISR return operation for 6 cycles before exiting, the ISR of the tail chain is executed.
3 CortexM3 and ARM7 interrupt controller comparison
In the past decade, ARMv4-based ARM7 series microcontrollers have been widely used in various fields. In the ARM7 series, there is no independent service for interrupts, but the effective interrupt response and interrupt handling mechanism is exchanged by sacrificing the performance of the processor. CortexM3's highly coupled NVIC enables hardware interrupt handling while supporting late and tail chain mechanisms, speeding up exception response and maximizing processor performance.
Figure 4 shows the differences in the structure of the interrupt controller between CorexM3 and ARM7.
It can be seen that the NVIC is directly integrated as part of the CortexM3 processor and integrated inside the processor core. The VIC is only free on the periphery of the ARM7 core, which inevitably occupies the kernel resources and affects the processing speed. The differences in functionality and implementation of the CortexM3 and ARM7 interrupt controllers are listed in Table 2.
3.1 The processor responds to a single exception
The CortexM3 and ARM7 exception handling process is shown in Figure 5.
Among them, TARM7 is the time overhead for ARM7 to handle exceptions; TARM7_PUSH and TARM7_POP are the stacking and popping operation time of ARM7; TCoretxM3 is the time overhead for CortexM3 to handle exceptions; TM3_PUSH and TM3_POP are the operation time for stacking and popping of CortexM3.
It can be seen that the CortexM3 processor uses 18 cycles less due to the processor state hardware save, which saves 42.8% of the overhead.
3.2 Processor response is late for abnormal
The difference between CortexM3 and ARM7 in dealing with late high priority exceptions is shown in Figure 6.
When IRQ2 is saving the processor state for ISR2 execution, a higher priority exception IRQ1 is reached. At this point ARM7 continues to push the stack. After the push operation is completed, ARM7 continues to perform the ISR1 push operation and then executes ISR1. In fact, the contents of the two push operations are the same. Therefore, CortexM3 optimizes the operation of this stage, introduces the late exception technique, and only performs the push operation once. And after the execution of ISR1 is completed, CortexM3 does not perform the pop operation, but directly enters the execution of ISR2 through a 6-cycle tail chain.
Among them, TARM7_later and TM3_later are the time overhead for ARM7 and CortexM3 to deal with late exceptions respectively; Ttailchaining is the time taken by CortexM3 to process the tail chain.
It can be seen from the calculation that the CortexM3 uses 44 cycles less, saving 65% of the abnormal overhead.
3.3 processor processing back to back exception
If a new exception arrives when the last exception register is popped, the processing of ARM7 and CortexM3 is quite different. The difference between CortexM3 and ARM7 in handling back to back exceptions is shown in Figure 7. ARM7 continues the current pop operation. After the pop operation is completed, the processor performs a push operation for executing ISR2, and then executes ISR2. In fact, the contents of the processor popup and the push stack are the same at this time. CortexM3 also optimizes the operation of this stage, introducing a tail chain mechanism. When IRQ2 arrives, CortexM3 immediately suspends the 8-stack pop operation, and then performs the tail chain operation, and then executes ISR2.
Among them, TARM_btb and TM3_btb are the time overheads used by ARM7 and CortexM3 to process back to back exception conversion respectively; Tcancel is the time when CortexM3 has been used for state recovery when the tail chain occurs.
It can be seen from the calculation that the CortexM3 uses 28 cycles less. In fact, the CortexM3 processor's minimum overhead for ISR1 to ISR2 conversion can be optimized to only 6 cycles, which greatly improves the back to back exception response capability.
Conclusion
This article describes the exception handling mechanism of the CortexM3 processor. By comparing with ARM7, the advantages of CortexM3 in exception handling are quantitatively analyzed, and there will be some reference and help for engineers using CortexM3 exception handling.
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