ISP image processing chip

1. Introduction to FH8510ISP processing chip

The FH8510 is an image signal processing chip for CIS (CMOS ImageSensor). It has a powerful image processing engine, CMOS image sensor interface, TV encoder, D/A converter, NTSC/PAL output, and ITU.BT65610Bit. The output is mainly applied to low-end standard-definition analog CCTV cameras, car rear-view cameras and building intercom cameras. The FH8510 can support a variety of CMOS image sensors with low power consumption, high resolution, flexible configuration, and high customization. The default configuration of the FH8510 can support OV7740, OV7725, and more CMOS image sensors can be configured via external EEPROM. The OSD of the FH8510 uses hardware image data decompression technology, and all OSD data can be placed in the EEPROM. The FH8510 provides an IRLED and IRCUT control interface that allows the user to set the on and off thresholds.

ISP image processing chip

2, FH8510 internal block diagram

ISP image processing chip

2.1, video input

Support SVGA, D1, VGA input

RGBBayer

Maximum data bit width 10-bit

Clock positive and negative edge sampling configurable

Frame valid, line valid signal polarity configurable

Highest pixel clock 54MHz

2.2, image processing (ISP)

RGBBayer data format, sensor output window coordinates are free

Automatic color to black and white

Fixed mode noise cancellation

Automatic detection and elimination of dead pixels

Sensor column fixed mode noise cancellation (external 4KB EEPROM)

Vignetting compensation (LensShadeCorrecTIon)

Lens center position configurable

Compensation coefficient table configurable

Automatic black bottom elimination

Adaptive 2D denoising

Image information statistics

Number of statistics windows, location and size configurable

The maximum number of statistical windows is 64

Provide the maximum, minimum, and mean values ​​for each window

Automatic exposure, 50Hz/60Hz flicker elimination

Automatic white balance

Edge detection based CFA interpolation

Automatic color correction for configurable color space conversion RGB2RGB

Gamma correction, gamma table configurable

Image enhancement

Degree contrast, hue and saturation adjustment

Image sharpening (5x5 filtering, strength can be matched)

Image scaling

Configurable zoom core, support for stepless scaling, matching the output and standard definition of the Sensor

Horizontal and vertical scaling configurable

Supports 64 phases, initial phase independent configurable

Image Resolution

VGASensor, 420TVL

D1, SVGASensor, 540TVL

2.3, video output

Composite video CVBS (NTSC720 & TImes; 480PAL720 & TImes; 576)

ITU.BT-656 (10Bit) output (optional)

2.4, OSD

1 Graphic layer overlay (external 8K EEPROM)

Graphic window position configurable

Graphic window height and width configurable

Graphic data format configurable (supports lossless compression 1~6bpp index bitmap)

Palette content configurable, supports up to 64 color 32bit color palette (ARGB8888 format)

Hardware flashing display control

Hardware Graphic Data Decompression

Hardware Graphic Data DMA Transfer Handshake

2.5, clock

6MHz crystal

2.6, EEPROM configuration

2KBYTE supports multiple CMOS image sensor configurations

4KBYTE supports multiple CMOS image sensor configurations and column fixed mode noise cancellation

8KBYTE supports multiple CMOS image sensor configurations, column fixed mode noise cancellation, OSD

3, typical application

The occasions that can be used include building intercom, security monitoring, and rear view system, as shown in the following block diagram:

ISP image processing chip

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