Due to the update of the development tools, it is necessary to repeat the previous content in this blog. Today we will first demonstrate how to use Vivado to develop pure logic projects, that is, to develop only on PL. Just recently, I saw Lei Silei's "Step by Step Core - Soft Core Processor Internal Design Analysis", so I moved some experiments to ZED-Board for verification. Children's shoes that are of interest to OpenRISC can focus on Rill's column for further learning resources.
First, a brief introduction to OpenRISC software development, with reference to the steps to establish a development environment on Lei Silei.
1. Download the GNU development environment, you can directly download the configured VirtualBox image, the link is ftp://openrisc.opencores.org/virtualbox-image/, the FTP username and password are openrisc. Download the 2011-12-15 version.
2. Download and install VirtualBox. New virtual machine, configured as Linux, Ubuntu, 512MB memory (not demanding), using existing virtual hard disk (OpenRISC_Ubuntu_2011-12-15.vdi)
The installation is complete and ready to start. The GNU toolchain is or32-elf-... (can be ar, as, g++, gcc, etc.). Root password: openrisc
Set the shared folder of Windows and virtual machine in VirtualBox. Close Ubuntu system, select "Settings" in the main interface of VirtualBox, add the Windows shared folder E:\Share in "Data Space", and name in Share in Ubuntu. After the setup is complete, start the Ubuntu system and enter the command sudo mount -t vboxsf Share /mnt/sharefolder
After the virtual machine is running, if the image is too large to be complete, you can right click and save it as a picture and view it locally.
3. Write a simple test assembly code example.s
# Comments like this
# Begin
.secTIon .text, "ax"
.org 0x100
.global _start
_start:
L.andi r0,r0,0
L.extwz r1,r0
L.extwz r2, r0
L.addi r1, r1, 0x0A
L.add r2,r2,r1
L.nop 0x0001
# End
4.
Compile: or32-elf-as example.s -o example.o
Link: or32-elf-ld -T ram.ld example.o -o example.or32
The link input script ram.ld reads as follows:
MEMORY
{
Ram : ORIGIN = 0x00000000, LENGTH = 0x00005000
}
SECTIONS
{
.text :
{
*(.text)
} > ram
.data :
{
*(.data)
} > ram
.bss :
{
*(.bss)
} > ram
}
ENTRY (_start)
OR1KSim simulator running: sim -t example.or32 -m1M > example.trace
The generated trace file example.trace is as follows:
Seeding random generator with value 0x88a2d16e
Or1ksim 2011-08-15
Building automata... done, num uncovered: 0/213.
Parsing operands data... done.
ResetTIng PIC.
Loadcode: filename example.or32 startaddr=00000000 virtphy_transl=00000000
Not COFF file format
ELF type: 0x0002
ELF machine: 0x005c
ELF version: 0x00000001
ELF sec = 5
SecTIon: .text, vaddr: 0x00000000, paddr: 0x0 offset: 0x00002000, size: 0x00000118
S 00000100: a4000000 l.andi r0,r0,0 r0 = 00000000 flag: 0
S 00000104: e020004d l.extwz r1,r0 r1 = 00000000 flag: 0
S 00000108: e040004d l.extwz r2,r0 r2 = 00000000 flag: 0
S 0000010c: 9c21000a l.addi r1,r1,0xa r1 = 0000000a flag: 0
S 00000110: e0420800 l.add r2,r2,r1 r2 = 0000000a flag: 0
Exit(0)
@reset : cycles 0, insn #0
@exit : cycles 5, insn #6
Diff : cycles 5, insn #6
From the above results, you can see the results of the software simulation, pay attention to the changes in the values ​​of r1 and r2, which will be seen later in the hardware simulation.
Export binary: or32-elf-objcopy -O binary example.or32 mem.bin
For the specific meanings of the above steps and command line parameters, please refer to the original book, which is omitted here.
In order to convert the mem.bin file into a format that Vivado Simulator can recognize, the blogger wrote the format conversion program bin2mem.m with matlab. The code is as follows:
Clear;
Clc;
Close all;
Fid = fopen('mem.bin','rb');
Mem = fread(fid,'uint8');
Fclose(fid);
Mem = reshape(mem,4,[]);
Mem = [65536*256,65536,256,1]*mem;
Fid = fopen('mem.data','w');
Fprintf(fid, '%08x', mem);
Fclose(fid);
After the mem.data is obtained, the end of OpenRISC software development is announced. The following is a hardware platform development using Vivado.
First get the Vivado 2013.2 software, which can be downloaded from the xilinx website. The latest version of the blogger has not used it, and cannot guarantee that all the steps are the same, and the reader needs to coordinate it.
After the installation is complete, run Vivado, double-click the icon below, the IDE on the left and the HLS on the right. This experiment only uses the IDE.
After launching, the welcome interface is as follows
Select Create New Project and set the project name as follows
Keep pressing the next step until after the following screen
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