BGA, TAB, parts, packaging and Bonding process

BGA, TAB, parts, packaging and Bonding process

1.AcTIve parts (Devices) Active parts refer to various active integrated circuits or transistors of semiconductor type, and there are other Passive-Parts passive parts, such as resistors and capacitors.

2, Array arrangement, array refers to the hole position of the through hole, or the surface of the pad, the grid is placed on the board surface (that is, matrix) array case. The common part of the "pin grid arrangement" is called PGA (Pin Grid Array), and the other "pin grid arrangement" is called BGA (Ball Grid Array).

3. ASIC-specific integrated circuit devices
ApplicaTIon-Specific Integrated Circuit, such as TV, stereo, VCR, camera, and other special-purpose ICs.

4. Axial-lead Axial-lead is a conventional cylindrical resistor or capacitor that is pulled out from the center of both ends to be inserted into the through-hole of the board to complete its overall function.

5, Ball Grid Array ball foot array (package)
It is a pin package of a large component, similar to the four-sided pin of QFP, which is connected to the board by SMT solder paste soldering. The difference is the "one-space" single-row pins listed around, such as the gull-winged feet, the flat feet, or the J-shaped feet that retract the bottom of the abdomen; change to a full array or partial array of the bottom of the abdomen, The distribution of the solder ball feet of the second space is adopted as a solder interconnection tool for the chip package to the circuit board. BGA is a packaging method developed by Motorola in 1986. It was first made of BT organic sheet into a double-sided carrier (Substrate), which replaces the traditional metal frame (Lead Frame) to package the IC. The biggest advantage of the BGA is that the Lead Pitch is much looser than the QFP. Many QFPs have been tightened to a distance of 12.5mil or even 9.8mil (such as the 320-pin CPU on the Daughter Card used in the P5 notebook). The pad is that the solder on the bare copper pad surface is under the Super Solder method, which makes the PCB manufacturing and downstream assembly very difficult. However, if the CPU of the same function is changed to the BGA mode of the full square array of the base of the abdomen, the foot distance can be relaxed to 50 or 60 mil, which greatly eases the technical difficulties of the upstream and downstream. At present, BGA can be divided into five categories, namely: (1) P-BGA (double-sided and multi-layer) of plastic carrier board (BT), which has been mass-produced in China. (2) C-BGA of ceramic carrier (3) T-BGA (4) packaged in TAB mode is only slightly larger than the original chip. Ultra-small m-BGA (5) Other special BGA, such as D- of Kyocera Bga (Dimpled), OL's M-BGA and Prolinx's V-BGA. The latter is particularly worth mentioning because its products are first produced domestically and are very difficult. The method uses a silver paste as a conductive material for interlayer interconnection, and a V-BGA (Viper) made by a build-up method. The carrier has two layers of copper sheets having a thickness of 10 mil or more for heat dissipation. Layer, it can be used as a high power (5 ~ 6W) large IC package.

6. Bare Chip Assembly The chip that is cut from the completed wafer is not packaged in the traditional IC, but the chip is directly assembled on the board, which is called Bare Chip Assembly. The early COB (Chip on Board) approach was the specific use of the nude chip, but the COB was glued to the back of the chip and then lined and sealed. The new generation of Bare Chip is also omitted from the line. It is the Flip Chip method, which is the direct contact and fusion of the electrode points on the front side of the chip. Or the bump of the chip is fastened to the inner leg of the TAB, and then the outer leg is connected to the PCB. These two new assembly methods are called "naked chip" assembly, which can save about 30% of the overall cost.

7. Beam Lead The ray-type parallel dense pin refers to the "Tape-Automatic Bonding" (TAB) type carrier pin, which can directly solder the bare chip to the inner leg of the TAB, and then solder the external leg to the circuit. On the board, this beam-parallel densely packed pin as a chip carrier is called Beam Lead.

8. Bonding Wire Bonding wire refers to the metal wire that is electrically integrated between the chip and the pin built in the IC. The common wire is gold wire and aluminum wire, and the diameter is between 1-2mil.

9. Bump bumps refer to small bumps, such as the various Solder Bump methods in DuPont's SSD process (SelecTIve Solder Deposit), a use of "bumps" (see Circuit Board Information Magazine for details). 48 issues P.72). In addition, in the assembly process of the TAB, there are many small solder or gold "bumps" (area of ​​about 1μ2) on the periphery of the circuit surface on the chip, which can be used to buckle the corresponding inner leg of the TAB. To complete the interconnection of "chip" and "carrier" (PCB) pads. The role of this "bump" is of paramount importance, and this process has not yet been promoted in China.

10. Bumping Process The bump process refers to the fabrication of tiny solder bumps (or gold bumps) on the finished wafer surface to facilitate downstream packaging and assembly processes such as TAB and Flip Chip. Such tiny bumps with a size of about 1 mm are very difficult to fabricate, and have not yet been put into production in China.

11. C4 Chip Joint, C4 chip soldering uses a combination of tin-lead gold (63/37) to form a high-temperature soft-collapsed convex ball, which is fixed on the back of the chip or on the front side of the circuit to "directly install" the downstream circuit board. (DCA), called chip soldering. C4 is a process that IBM introduced more than 20 years ago. It was originally referred to as "Controlled Collapsed Chip ConnecTIon" and is now widely used for P-BGA assembly on motherboards. Soldering is another area of ​​soldering other than chip bonding.

12. Capacitance Capacitance When there is a potential difference between the two conductors, the stored energy will be collected in the medium, and some "capacitance" will appear. Its mathematical expression C = Q / V, that is, capacitance (Fara) = electricity (Coulomb) / voltage (volts). If the two conductors are parallel plates (area A) and the distance d is, and the dielectric constant (Dielectric Constant) of the material is ε, then C = εA / d. Therefore, when A and d are constant, the lower the dielectric constant, the smaller the capacitance will appear between them.

13. The Castalation-type integrated circuit device is a porcelain package with a leadless large-scale chip (VLSI), which can be soldered by using a metal pad in each of the ports and a pad on the corresponding board surface. This type of IC is less used for general commercial electronic products and is only used on large computers or military products.

14. Chip Interconnection chip interconnect refers to the chip of the heart part of a semiconductor integrated circuit (IC), which is interconnected before being packaged into a complete part. The traditional chip interconnection method is performed by wire bonding between each electrode point and pin; followed by "tape automatic bonding" (TAB) method; and the most advanced "clip method" (Flip Chip). The latter is a near-die size package (CSP) with very high precision.

15. Chip on Board The chip-on-board is a chip that integrates the chip of the integrated circuit with silver-containing epoxy glue directly on the board and then "wire bonding" through the pins. A suitable anti-sag epoxy resin or silane (Silicone) resin seals the COB region, thus eliminating the cost of packaging the integrated circuit. Some consumer-grade electronic pens or electronic watches, as well as various timers, can be manufactured in this way. The sub-micron ultra-fine line is a wafer obtained from aluminum film vacuum evaporation, precision photoresist, and precision plasma etching (Plasma Etching). After the wafer is diced to obtain a separate chip, and the die is continuously soldered at the center of the fixed frame, the common IC can be obtained by wire bonding, packaging, and bending. The large-scale IC (VLSI) with four-sided pin is also called "Chip Carrier chip carrier", and the new TAB is also a "chip carrier" without prior packaging. Since the prevailing of SMT, the resistors and capacitors that should be inserted in the original, in order to save the board assembly space and facilitate automation, the packaging method of the horizontal shaft pin has been changed to a small sheet-like body. Also known as chip resistor Chip Resistor, or chip capacitor Chip Capacitor. In addition, Chips refers to the collapse of the first cutting edge of the drill tip portion of the drill, which is called Chips.

16, Chip On Glass crystal glass (COG) (direct mounting of chip to glass circuit board)
In a liquid crystal display (LCD) glass circuit, each of the ITO (Indium Tin Oxide) electrodes must be interconnected with a plurality of driving ICs on the circuit board to perform the development function. At present, all kinds of large ICs still use QFP packaging methods. Therefore, QFPs must be installed on the PCB first, and then conductive adhesives (such as Ag/Pd paste, Ag paste, unidirectional conductive adhesive, etc.) are interconnected with the glass circuit board. . The new approach is to fasten the driver IC for the large-scale IC (Driver LSI) directly to the ITO electrode point of the glass plate by the "flip-chip" method, which is called the COG method. It is a very advanced assembly technology. Similar arguments include COF (Chip on Film) and the like. Conformal Coating, the board that protects the finished parts, in order to protect the shape of the whole board, and then seal it with insulating coating for better reliability. This type of profile is used in general military or higher-level assembly panels.

17, Chip die, chip, chip-like integrated circuit (IC) package at the heart of the location, are equipped with line-dense die (die) or chip (Chip), this small "line piece", It is cut from a multi-piece wafer (Wafer).

18, Daisy Chained Design The design of the chrysanthemum ring refers to the square ring design consisting of the tight arrangement of the "moment pads" around it, like the garland of the chrysanthemums. Common ones are electrode pads on the periphery of the chip, or pads of various QFP pads on the board surface.

19. Device Electronic component refers to a basic electronic component that can perform independent functions on a separate entity and cannot be further distinguished by its destruction.

20, Dicing chip segmentation refers to the semiconductor wafer (Wafer), with a diamond knife cut into a complete chip (Chip) or die (Die) unit of the circuit system, the process of division is called Dicing.

21. The Die Attach die mount will complete the test and cut good die and be mounted on the externally interconnected lead frame system in various ways (such as the traditional Lead Frame or the new BGA carrier), called " An Jing". Then, the wires are interconnected from the output points of the die and the tripod leads, or directly combined with a flip chip Flip Chip to complete the package of the IC. The above-mentioned "die mounting" was carried out in the early stage by combining the gold plating layer on the back side of the chip with the gold plating layer on the tripod, and combining it with TC Bond or UC Bond, so it is called Die Bond. However, in order to save gold plating and the new process of "direct die mounting" (DCA or COB) for the board surface, the silver-containing thermal conductive adhesive has been used instead of the gold-plated layer to be welded, so it is called "Die Attach".

22. Die Bonding die
Die also refers to the heart of the integrated circuit, which is a small piece of "grain" that is cut from the wafer (wafer), with the gold layer on the back side and the gold-plated surface in the center of the Lead Frame. Thermo Compression Bonding (TCBonding) for instant high temperature. Or fixed by epoxy resin, called Die Bond, to complete the first step of IC internal circuit packaging.

23. A Diode diode is a type of semiconductor component "Transistor". It has two ends connected to a mother body. When the polarity of the applied voltage is different, different conductor properties will also be exhibited. Another "light-emitting diode" can replace the light-emitting points of various colors on the instrument panel, which is more energy-saving and durable than the general light bulb. At present, most of the diodes have been changed to the SMT form, and the figure shown in the figure is the anatomical map of SOT-23.

24, DIP (Dual Inline Package) double-row package refers to a part with two rows of symmetrical pins, which can be inserted in the double-row symmetric foot holes of the circuit board. Parts of this type are mostly in the early days of various ICs, and some "mesh resistors" are also used.

25. Discrete Component Bulk parts refer to general small passive resistors or capacitors, which are different from integrated circuits with active part functions.

26, Encapsulating Encapsulation, capsules in order to waterproof or prevent the impact of air, some items are sealed and isolated from the outside world.

27. End Cap The head refers to some small chip resistors or chip capacitors of SMD. Both ends can be used as conductive and soldered metal parts, called End Cap.

28, Flat Pack flat package (parts)
Refers to thin parts, such as small special IC type, which has parallel pins on both sides, which can be flatly welded on the board surface, so that the volume or thickness of the assembly can be greatly reduced. It is mostly used in military products and is the first of SMT.

29, Flip Chip flip chip, buckle crystal chip directly on the board side of the reverse buckle, early called Facedown Bonding, is a protruding metal joint (such as Gold Bump or Solder Bump) as a connection tool. Such raised contacts can be placed on the chip, or on the surface of the board, and then interconnected by C4 soldering. It is a technology (DCA or COB) in which the chip is directly packaged and assembled on the board surface.

30. Four Point Twisting Four-point distortion method This method is an external force test method for some large-scale QFPs that are bonded to the surface of the board. That is, the support points are arranged at two opposite corners of the board, and pressure is applied to the other two diagonals to force the board to be distorted, and the strength of each solder joint is observed from the relationship between the amount of deformation and the magnitude of the pressure.

31. Gallium Arsenide (GaAs) Gallium arsenide is a substrate material for common semiconductor circuits. Its chemical symbol is GaAs, which can be used to fabricate high-speed IC components at a faster rate than silicon-based chip substrates.

32. Gate Array gate array, the gate element is the basic element of semiconductor products, refers to the electrode of the control signal inlet, which is customarily called "gate".

33. The Glob Top dome package refers to an arc-shaped encapsulant that is directly mounted on a chip-on-board (Chip-On-Board) or its construction method. The sealant used is epoxy resin, silicone resin (Silicone, also known as silicone) or a mixture thereof.

34. Gull Wing Tead This small, outwardly extending double row of feet is designed for surface mount SOIC packaging and was first developed in 1971 by the Dutch company Philips. The shape of the body and the pin is very similar to that of a seagull, hence the name "gull wing". Its form factor is currently standardized under JEDEC's MS-012 and -013 specifications.

35. Integrated Circuit (IC) Integrated circuit devices are arranged on multiple layers of the same sheet substrate (silicon material), and are arranged with many tiny electronic components (such as resistors, capacitors, semiconductors, diodes, transistors, etc.), as well as various tiny mutual Integrated electrical components, such as Interconnection conductor lines, are referred to as ICs.

36, J-Lead J-type pin is the standard pin method of PLCC (Plastic Leaded Chip Carrier) "plastic crystal (core) chip carrier" (VLSI), due to the large surface of this double-sided pin or four-sided foot connection The adhesive component has the advantages of considerable board area saving and easy cleaning after soldering, and the strength of each pin before soldering is also very good and not easily deformed, which is easier to maintain than another Gull Wing Lead method. "Coplanarity" has become the best way for high-volume SMDs in packaging and assembly.

37. Lead pin, pin electronic components When you want to take root assembly on the board, you must have a variety of pins to complete the welding and interconnection work. Early pin-multi-socket soldering type has gradually changed to surface-mount (SMD) soldering pins due to increased assembly density in recent years. There is also a "no lead" but a specific solder joint on the part package for surface soldering, which is a Leadless part.

38. Known good chips from Known Good Die (KGD)
The chip of the IC can be called Chip or Die. There are many chips on the finished wafer (Wafer), and the quality is good or bad. After the life test (Burn-in Test is also called aging test), it is known. A chip with good electrical properties is called KGD. However, the definition of KGD is quite different. Even if the same company has different customers for different products or the same product, its definition is difficult to be consistent. A representative statement is: "A certain chip has good electrical quality after aging and electrical measurement. After continuous production and packaging for more than one year, it can still maintain its yield at 99.5% or more. This chip can be called KGD."

39. Lead Frame All kinds of electronic components with sealed body and multiple pins, such as integrated circuit (IC), mesh resistor or simple diode triode, etc., the main body and each pin before packaging The temporarily fixed metal frame is called the Lead Frame. This term is also known as the fixed frame or the stand. The packaging process is to fix the central part of the chip (Die, or Chip chip) with a gold or silver layer on the back side, which is fixed by a high-temperature welding method and a gold-plated layer at the center of the stand, called Die Bond. Another gold wire or aluminum wire is connected from the solid chip to each pin, called Lead Bond. Then the entire body is sealed with plastic or ceramic, and the outer frame of the tripod is cut and further bent to form the desired components. Therefore, the "foot stand" plays an important role in the electronic packaging industry. Commonly used alloy materials include Kovar, Alloy 42 and phosphor bronze. The forming methods include die punching and chemical etching.

40, Lead Pitch pitch refers to the distance between the various pin centerlines of the parts. The early jacks are all 100 mil standard pitch, and the QFP pitch of the SMT is now densely assembled. The initial 50 mil is tightened again and again, after 25 mils, 20 mils, 16 mils, 12. 5 mils to 9.8 mils. It is generally considered that the pitch of the foot below 25 mil (0.653 mm) is called Fine Pitch.

41. Multi-Chip-Module (MCM) Multi-Chip (Chip) Module This is another microelectronic product that has only been developed since 1990. It is similar to IC cards or Smart cards for small circuit boards. However, the difference between MCM is that various ICs that have not been packaged are assembled on the circuit board in the form of "Bare Chips" directly using the traditional "Die Bond" or the new Flip Chip or TAB. Just like the electronic pen that installed a chip directly on the board in the early days, it needs to be lined and sealed, called COB (Chip On Bond). But today's MCM is a lot more complicated, not only with multiple chips on the multi-layer board, but also directly combined with "bumps" instead of "wires". It is a high-end microelectronic assembly. MCM is defined as a direct assembly of a bare chip without a wire on a small board surface, and its chip occupies more than 70% of the total board area. There are three types of this typical MCM (currently it seems to have the most potential of D type): MCM-L: It is still using Laminates of various materials of PCB, and its manufacturing design and method are exactly the same as PCB. It's just a lighter, thinner one. At present, IC cards can be made in China, and those with a line width of 5 mils to 10 mils will be able to produce such MCMs. However, due to the need to play the chip and the relationship of wire bonding or reverse buckle welding, the gold-plated "bump" must have a purity of 99.99%, and the area is smaller to 1 micron square, which is more difficult. MCM-C: Ceramic substrate with modified hybrid circuit (Hybrid), is a porcelain multilayer board (MLC), the circuit is similar to Hybrid, all with thick film printing gold paste or The palladium paste silver paste is made into a circuit, and the assembly of the chip is also carried out by a reverse flip chip method. MCM-D: The multilayer structure of the circuit layer and the dielectric layer is a thin film method using a deposited method or a line transfer method of Green Tape, and the conductor and the medium are successively laminated on the bottom of the porcelain or high molecular material. On the material, and become a combination of multi-layer boards, this MCM-D is the most accurate of the three.

42. OLB (Outer Lead Bond) external pin combination is a "tape automatic bonding" TAB (Tape Automatic Bonding) technology in a process station refers to the TAB assembly peripheral four externally facing pins, respectively, and the circuit board The corresponding pads are soldered and referred to as "outer pin bonding." The TAB assembly also has four inward-facing pins for connecting the integrated circuit chip (Chip or chip) inwardly, called internal pin bonding (ILB), in fact the inner and outer scripts. Come is one. Therefore, the TAB technology is simply a four-sided internal and external pin as a "bridge", and the complex IC chip semi-finished products are directly combined on the circuit board by the OLB method, thereby eliminating the trouble of the conventional IC pre-packaging.

43. Packaging package, the term "package" refers to a variety of electronic components, to complete its "sealing" and "forming" series of processes. However, if the expansion extends its meaning, then until the completion of the mainframe computer, all kinds of manufacturing work can be called "Interconnceted Packaging". If the electronic kingdom is divided into many levels of hierarchy (Hierarchy), the various levels of electronic assembly or assembly, from small to large, will be: Chip (chip, chip manufacturing), Chip Carrier (single product of integrated circuit) Package), Card (small circuit board assembly), and Board (regular board assembly) and other four levels, plus "system configuration" there are five levels.

44, Passive Device (Component) passive components (parts)
Refers to some resistors (Resistor), capacitors (Capacitor), or inductors (Incuctor) and other parts. When they are applied with electronic signals, they are still original intentions without changing their basic characteristics, which are called "passive parts"; relative active devices (such as transistors (Tranistors), diodes (Diodes) or Electron tube (Electron Tube) and the like.

45, Photomask reticle This is the term used in the microelectronics industry, refers to the glass film used in the wafer imaging of Wafer. The dark area of ​​the sunscreen may be the latex of the general film, or it may be extremely thin. Metal film (such as chromium). This type of reticle can be imaged on a "silicon wafer" coated with photoresist, which is similar to a PCB except that the line width is reduced to a micron (1 to 2 μm) level or even a sub-micron level (0.5 μm). The accuracy is 100 times smaller than the thinnest line on the board. (1 mil = 25.4 μm).

46. ​​Pin Grid Array (PGA) matrix pin package refers to a complex package. The reverse side is a pin-shaped upright pin with matrix grid points, which can be inserted into the through holes of the circuit board. The front side has a multi-layer chip package interconnect area that is recessed in the middle, and more I/O pins can be placed than the "Dual Row Pin Package" (DIP). The drawings are schematic and physical maps.

47. Popcorn Effect The popcorn effect originally refers to an IC packaged in a plastic outer body. The silver paste used for chip mounting will absorb water. Once the plastic body is sealed without precaution, when the downstream assembly welding encounters high temperature, The moisture will cause the explosion of the seal due to the vaporization pressure, and at the same time it will emit a sound like a popcorn, hence the name. Recently, the package components of P-BGA are very popular, not only the silver glue will absorb water, but also the BT substrate of the serial board will absorb water, and the popcorn phenomenon often occurs when the management is poor.

48, Potting casting, mold sealing refers to various electronic assemblies that will be easily deformed and damaged, or must be isolated, first placed in a specific mold or cavity, filled with liquid resin, after hardening The Potting method can be used by solidifying the circuit pack body and filling the gaps therein for isolation protection, such as packaging of TAB circuits, integrated circuits, or other circuit components. Potting is very similar to Encapsulating, but the former emphasizes that there are no defects in the interior of the solid seal (Voids).

49. Power Supply refers to a device that can supply electrical power to another unit, such as a transformer (Transfomer), a rectifier (Rectifier), a filter (Filter), etc., which can convert AC power into DC power, or A device that maintains a constant input voltage within a certain limit.

50. Preform pre-products often refer to various packaging materials or welding metals. For the convenience of construction, the raw materials are first made into a shape that is easy to control, such as making hot melt glue into small pieces or small pieces. It is convenient to weigh the weight for melting and blending. Or the glass used for the sealing of the porcelain IC is first made into a bead shape, or the solder is first made into a small ball bead shape, so as to be adjusted into a solder paste (Solder Paste), etc., which are called Preform.

51. Purple Plague Purple Plague When gold and aluminum are in close contact with each other for a long time and exposed to moisture and high temperature (above 350 °C), a purple common compound formed between the interfaces is called Purple Plague. This kind of "violet plague" has brittleness, which causes the "joining" between gold and aluminum to collapse. This phenomenon is more likely to generate "ternary" when there is silicon (Silicone) nearby (Ternary The common compound accelerates deterioration. Therefore, when the gold layer must be in intimate contact with the aluminum layer, a "barrier" should be added to prevent the formation of the complex. Therefore, in the "bumping" process upstream of the TAB, each aluminum pad on the surface of the chip must be first or two layers of titanium, tungsten, chromium, nickel, etc. as a barrier layer. Guarantee the fixing force of the bumps. (See Board Information Magazine, Issue 66, P.55).

52. The Quad Flat Pack (QFP) square flat package refers to a general term for a "large scale integrated circuit device" (VLSI) having a square body and a four-sided pin. This type of large IC for surface bonding can be divided into J-type pins (also used for SOIC on both sides of the foot, easier to maintain Coplanarity of each pin), Gull Wing ), flat feet and no-foot type. In normal oral or textual expressions, QFP is used as an abbreviation, and there is also a spoken term called Quad Pack. The mainland industry calls it "large-scale accumulation."

53. Radial Lead The radial pin means that the part's pins are scattered from the side of the body, such as various DIP or QFP, which are different from the Axial lead that protrudes from the ends of the part.

54. The Relay relay is a special control component like an active contact. When the current passing through a certain "set value", the contact will be disconnected (or turned on), and the current will be "interrupted and renewed". Actions that deliberately affect the operation of components in the same circuit or other circuits. According to the principle and structure of its manufacture, various types of relays, such as electromagnetic coil, semiconductor, pressure type, bimetal sensible heat, photosensitive type and reed switch, are important components in motor engineering.

55. Semi-Conductor semiconductor refers to a solid substance (such as Silicon) whose resistivity (Resistivity) is between a conductor and a resistor, and is called a semiconductor.

56. Separable Component Part A separable part refers to a part or accessory on the main body. There is no chemical bond between the part and the main body, and there is no additional protection film, welding or sealing compound (Potting Compound). Measures; making it detachable at any time, called "separable parts."

57. Silicon Silicon is a non-metallic element in the form of black crystals. Its atomic number is 14, and its atomic weight is 28, accounting for about 25% of the total weight ratio of surface materials. Its oxide silica is the main component of sand. The commercial process of pure silicon is to obtain 99.97% pure silicon crystals through the multiple reduction reaction of SiO2 through complex procedures. After cutting into thin slices, it can be used in the manufacture of semiconductor "wafer", which is the most important in the modern electronics industry. material.

58. The Single-In-line Package (SIP) single-sided pin package is a part package that only has a pin-shaped pin or a wire-type pin, which is called SIP.

59, Solder Bump solder bump chip (Chip) can be directly on the board surface of the Flip Chip on Board (Filp Chip on Board) to complete the chip and circuit board assembly interconnection. This reverse button COB flip chip method can save the process and cost of many chip packages. However, in addition to the PCB, the PCB and the board must be equipped with corresponding soldering bases. The corresponding points on the periphery of the chip itself must also be made of various round or square miniature "solder bumps". When the bump is placed only around the periphery of the "chip", it is called FCOB. If the bump is covered all over the entire surface of the chip, the flip-chip soldering method is called "Controlled Collapsed Chip Connection".

60, Solder Colum Package Tin column foot packaging method is a process developed by IBM. The ceramic package C-BGA is soldered and assembled on a circuit board with its high-column tin legs. The tin-lead ratio of the solder column is 90/10 and the height is about 150 mil. The solder paste can be soldered on the column base. This tin column is located between the PCB and the C-BGA. It has the effect of dispersing stress and heat dissipation. It is very advantageous for large ceramic parts (edge ​​length 35mm~64mm).

61. Spinning Coating Rotating and coating the photoresist on the wafer wafer (Wafer) surface, and adopting the auto-rotation coating method. The wafer is mounted on the self-rotating disc, and the emulsion is carefully poured on the center of the round surface, and then the balance between the Centrifugal Force and the adhesion is used to leave a uniform light on the circular surface. The coating method of the barrier film is called. This method can also be used for coating construction in other occasions.

62. Tape Automated Bonding (TAB) is a kind of chip that uses a multi-pin large-scale integrated circuit (IC). Instead of traditionally packaging it into a complete individual, it uses a TAB carrier. The unsealed chip is directly attached to the board surface. The soft tape of "Polyimide" and the inner and outer pins etched by the attached copper foil are used as carriers to allow the large chip to be first bonded to the "inner pin". After the automatic test, the board is assembled by "outer pin" to complete the assembly. This new type of assembly that combines packaging and assembly is called the TAB method. This TAB method not only saves the cost of IC pre-packaging, but also has a new hope for multi-foot and large-part assembly for multi-foot VLSIs with more than 300 feet. When it comes to SMT assembly, TAB will be a new hope for multi-foot assembly. Information magazine article 66 ().

63. Thermocompression Bonding is a kind of encapsulation method of IC. It is a very thin gold wire or aluminum wire, which is combined with the two wire ends of the chip (chip) by heating and pressing. On the inner legs of the lead frames, the combination of their functions is called "hot press bonding", referred to as TCBond.

64. Thermosonic Bonding refers to a method in which an integrated circuit device has a "wire bonding" between a chip and a pin. That is to say, the combination of heating and ultrasonic energy is called Thermosonic Bonding, referred to as TS Bond.

65, Thin Small Outline Packange (TSOP) thin small integrated circuit device small side of the gull wing "IC" (SOIC), the number of feet is about 20 to 48 feet, the width of the foot is 6 to 12mm, The foot distance is 0.5 mil. If used in PCMCIA or other hand-held electronic products, the thickness will be further reduced by half, called TSOP. This thin and small double-row IC can be divided into two types; TypeI is to extend outward from the two short sides, Type II is to extend outward from the two long sides.

66. Three-Layer Carrier Three-layer carrier This refers to the structure of the substrate of the "tape-belt automatic bonding" (TAB) type "chip carrier", which is composed of a flaky resin layer (usually a film of polyamine). The copper foil, and the three layers of the adhesive layer interposed therebetween, are called a Three-Layer Carrier. There is a relatively "two-layer carrier", that is, the TAB product from which the intermediate adhesive layer is removed.

67. Transfer Bump transfer type bump, transfer type block coil with automatic combined chip carrier, the combination of the inner pin and the chip must be at the fixed point of the chip, first make the required solder bump or Gold bumps, when combined with conductive points. One of the methods is to prepare the bumps on the other carriers, and then transfer the bumps to the inner legs before the chip bonding, so as to continue the integration with the chip. This kind of pre-made bump is called a "shifting bump".

68. The Transistor transistor is a semiconductor-type Active Components with more than three electrodes that perform rectification and amplification. The raw materials of the chip mainly use germanium and silicon, and deliberately add a little impurity to form a simple semiconductor such as a negative type (n Type) and a positive type (p Type), which is called a "transistor". Such Transistors are available in pin-in or SMT bonding.

69. Ultrasonic Bonding Ultrasonic wave combines the energy of the ultrasonic wave (about 10 KHz) and the mechanical pressure to complete the wire bonding operation on the IC semiconductor chip.

70. Two Layer Carrier Two-layer carrier This is also a new material for the "tape-type chip carrier", which is different from the three-layer carrier used in the industry. The biggest difference is that the middle layer of the adhesive is removed, leaving only the two layers of the "Polyimide" resin layer and the copper foil layer directly attached. Not only the thickness is thinner and more flexible, but also other properties. There are improvements, but it has not yet reached the point of mass production.

71. Very large-scale integration (VLSI) very large scale integrated circuit devices, the number of semiconductors (Transistor) accommodated in a single die (Die) is more than 80,000, and the width of the interconnected circuit is 1.5μ. (60 μin) or less, and such a chip having a very large capacity is packaged as a square IC having four sides and multiple pins, and is called VLSI. These VLSIs have various types of packages, such as J-shaped feet, gull-wing feet, flat long legs, and cast-type feet, depending on the way they are connected. At present, ICs with larger capacity pins (such as 250 feet or more) are becoming more and more difficult to install on the circuit. Therefore, the nude die is first mounted on the inner leg of the TAB carrier and then transferred to the PCB. Up; and directly splicing the die, or soldering it on the board surface, but it has not been popular in general electronic industrial production.

72. The Wafer wafer is a substrate for a "grain" or "chip" of a semiconductor component. From a high-purity silicon crystal column (Crystal Ingot) stretched out, the cut circular wafer is called a wafer. ". After that, a precise "mask" is used to obtain the desired "light resistance" through the photosensitive process, and then the silicon material is precisely etched into the groove, and the metal vacuum evaporation process is continued, and in the separate "grains or chips". (Die, Chip) completes its various micro components and fine lines. As for the back side of the wafer, a gold layer is additionally evaporated to serve as a die attach to the stand. The above process is called Wafer Fabrication.早期在小集成电路时代，每一个6吋的晶圆上制作数以千计的晶粒，现在次微米线宽的大型VLSI，每一个8吋的晶圆上也只能完成一两百个大型芯片。 Wafer的制造虽动辄投资数百亿，但却是所有电子工业的基础。

73、Wedge Bond楔形结合点半导体封装工程中，在芯片与引脚间进行各种打线；如热压打线TC Bond、热超音波打线TS Bond、及超音波打线UC Bond等。打牢结合后须将金线末端压扁拉断，以便另在其它区域继续打线。此种压扁与拉断的第二点称为Wedge Bond。至于打线头在芯片上起点处，先行压缩打上的另一种球形结合点，则称为Ball Bond。左四图分别为两种结合点的侧视图与俯视图，以及其等之实物体。Welding熔接也是属于一种金属的结合(Bonding)方法，与软焊(soldering或称锡焊)、硬焊(Brazing)同属"冶金式"(Metallugical)的结合法。熔接法的强度虽很好，但接点之施工温度亦极高，须超过被接合金属的熔点，故较少用于电子工业。

74、Wire Bonding打线结合系半导体IC封装制程的一站，是自IC晶粒(Die或Chip)各电极上，以金线或铝线(直径3μ)进行各式打线结合，再牵线至脚架(Lead Frame)的各内脚处续行打线以完成回路，这种两端打线的工作称为Wire Bond。

75、Zig-Zag In-Line Package (ZIP)链齿状双排脚封装件凡电子零件之封装体具有单排脚之结构，且其单排脚又采不对称"交错型式"的安排，如同拉链左右交错之链齿般，故称为Zig-Zag式。ZIP是一种低脚数插焊小零件的封装法，也可做成表面黏装型式。不过此种封装法只在日本业界中较为流行。

76、ASIC Application Specific Integrated Circuit
特定用途之集成电路器是依照客户特定的需求与功能而设计及制造的IC，是一种可进行小量生产，快速变更生产机种，并能维持低成本的IC。

77、BGA Ball Grid Array
矩阵式球垫表面黏装组件(与PGA类似，但为S MD)

78、BTAB Bumped Tape-Automated Bonding
已有突块的自动结合卷带指TAB卷带的各内脚上已转移有突块，可用以与裸体得片进行自动结合。

79、C-DIP Ceramic Dual -in-line Package
瓷质双祭脚封装体(多用于IC)

80、C4 Controlled Collapse Chpi connection
可总握高度的裸体芯片反扣熔塌焊接

81、CMOS Complimentary Metal-Oxide Semiconductor
互补性金属氧化物半导体(是融合P通路及N通路在同一片"金属氧化物半导体"上的技术)

82、COB Chip On Board
芯片在电路板上直接组装。是一种早期将裸体芯片在PCB上直接组装的方式。系以芯片的背面采胶黏方式结合在小型镀金的PCB上，再进行打线及胶封即完成组装，可省掉IC本身封装的制程及费用。早期的电子表笔与LED电子表等均将采COB法。不过这与近年裸体芯片反扣组装法(Flip Chip)不同，新式的反扣法不但能自动化且连打线(Wire Bond) 也省掉，而其品质与可靠度也都比早期的COB要更好。

83、CSP Chip Scale Package
晶粒级封装

84、DIP Dual Inline Package
双排脚封装体(多指早期插孔组装的集成电路器)

85、FET Field-Effect Tranistor
场效晶体管利用输入电压所形成的电场，可对输出电流加以控制，一种半导体组件，能执行放大、振荡及开关等功能。一般分为"接面闸型"场效晶体管，与"金属氧化物半导体"场效晶体管等两类

86、GaAs Gallium Arsenide (Semiconductor )
砷化半导体是由砷(As)与(Ga)所化合而成的半导体，其能隙宽度为1.4电子伏特，可用在晶体管之组件，其温度上限可达400℃。通常在砷化半导体中其电子的移动速度，要比硅半导体中快六倍。GaAs将可发展成高频高速用的"集成电路"，对超高速计算机及微波通信之用途将有很好的远景。

87、HIC Hybrid Integrated Circuit
混合集成电路将电阻、电容与配线采厚膜糊印在瓷板上，另将二极管与晶体管以硅片为材料，再结合于瓷板上，如此混合组成的组件称为HIC。

88、IC Integrated Circuit
集成电路器是将许多主动组件(晶体管、二极管)和被动组件(电阻、电容、配线)等互连成为列阵，而生长在一片半导体基片上(如硅或砷化等)，是一种微型组件的集合体，可执行完整的电子电路功能。亦称为单石电路(Monolihic Circuits)。

89、ILB Inner Lead Bonding
内引脚结合是指将TAB的内引脚与芯片上的突块(Bump ; 镀锡铅或镀金者)，或内引脚上的突块与芯片所进行反扣结合的制程。

90、KGD Known Good Die
确知良好芯片

91、LCC Leadless Chip Carrier
无脚芯片载体(是大型IC的一种)

92、LCCC Leadless Ceramic Chip Carrier
瓷质无脚芯片载(大型IC的一种)

93、LGA Land Grid Array
焊垫格点排列指矩阵式排列之引脚焊垫，如BGA"球脚数组封装体"，或CGA"柱脚数组封装体"等皆属之。

94、LSI Large Scale Integration
大规模集成电路指一片硅半导体的芯片上，具有上千个基本逻辑闸和晶体管等各种独立微型之组件者，称为LSI。

95、MCM Multichip Module
多芯片模块是指一片小型电路板上，组装多枚裸体芯片，且约占表面积70% 以上者称为MCM。此种MCM共有L、C及D等三型。L型(Laminates)是指由树脂积层板所制作的多层板。 C(Co-Fired) 是指由瓷质板材及厚膜糊印刷所共烧的混成电路板，D(Deposited)则采集成电路的真空蒸着技术在瓷材上所制作的电路板。

96、PGA Pin Grid Array
矩阵式插脚封装组件

97、PLCC Plastic Leaded Chip Carrier
有脚塑料封装芯片载体(胶封大型IC)

98、QFP Quad Flat Package
四面督平接脚封装体(指大型芯片载体之瓷封及胶封两种IC)

99、SIP Single Inline Package
单排脚封装体

100、SOIC Small Outline Intergrated Circuit
小型外贴脚集成电路器指双排引脚之小型表面黏装IC，有鸥翼脚及J型脚两种。

101、SOJ Small Outline J-lead Package
双排J型脚之封装组件

102、SOT Small-Outline Transistors
小型外贴脚之晶体管

103、TAB Tape Automatic Bonding
卷带自动结合技术是先将裸体芯片以镀金或镀锡铅的"突块"(Bump)反扣结合在"卷带脚架"的内脚上(ILB) ，经自动测试后，再以卷带架的外脚结合在电路板的焊垫上(OLB) ，这种以卷带式脚架为中间载体，而将裸体芯片直接组装在PCB上的技术，称为"TAB技术"。

104、TCP Tape Carrier Package
卷带载体封装(此为日式说法，与美式说法TAB"卷带自动结合"相同)

105、TFT Thin Film Transistor
薄膜式晶体管可用于大面积LCD之彩色显像，对未来之薄型电视非常有用。

106、TSOP Thin Small Outline Plackage
薄超型外引脚封装体是一种又薄又小双排脚表面黏装的微小IC，其厚度仅1.27mm，为正统SOJ高度的四分之一而已。

107、ULSI Ultra Large Scale Integration
超大规模集成电路

108、VHSIC Very High Speed Integrated Chips
极高速集成电路芯片

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