LMX2531 series products are widely used in wireless communication base station systems. Compared with integer frequency division, fractional frequency division can obtain better phase noise performance, but fractional frequency division will cause spur problems, especially integer boundary spurs are particularly prominent. This article introduces a way to improve the integer boundary spurs by up to 10dB on the basis of ensuring phase noise performance as much as possible.
1. Proposal of integer boundary spur problem of fractional frequency divider
Compared with the integer frequency division frequency synthesis technology, the fractional frequency division frequency synthesis technology generates a higher phase discrimination frequency through a smaller N frequency division ratio. Among them, the delta-sigma fractional frequency division technology is the most widely used. According to the following phase noise formula 1.1, it is known that a smaller frequency division N can improve the phase noise performance of the output signal, which is also the charm of the decimal frequency synthesis technology that has become popular in recent years.
On the basis of obtaining good phase noise performance, the spurs of the fractional frequency division technique are more complicated than the integer frequency division technique. TI's Dean Banerjee's application document 1879 "FracTIonal N Frequency Synthesis" has a very detailed explanation of the spur generation principle and the corresponding treatment countermeasures, so I won't make too much explanation here. For the most serious integer boundary spurs among the fractional spurs, the processing method in this paper is frequency point avoidance, which increases the complexity of the application of RF local oscillator in mobile communication base stations. This article takes the LMX2531 series widely used in the industry as an example, through the LMX25312080EVAL evaluation board, combined with the design simulation software clock design tool and register configuration software codeloader4, to optimize the design in the original design for integer boundary spurs, and finally get 10dB improvement.
2. Optimal design of integer boundary spurs for fractional dividers
Figure 1 is the original design designed using the clock design tool software. The loop bandwidth is 11 kHz and the phase margin is 42.4 degrees. Figure 2 is the topology of the loop filter, and Table 1 is the measured results of the phase noise and spurs of the circuit
Figure 1 LMX2531LQ2080 original design
Figure 2 Original design
Table 1 Original design performance test results
When the numerator is 1 or FDEN-1 spur, that is, the integer boundary spur, is the worst case of all spurs, especially as the GSM base station's transmit local oscillator, this spur of LMX2531 or higher order harmonic spur It will be transmitted through the mixer or IQ modulator and cannot meet the requirements of the emission spectrum template. By reducing the loop bandwidth, the suppression of @ 40kHz spurs is strengthened, but too small loop bandwidth will seriously affect the lock time of the phase-locked loop.
Try to change the loop parameters related to the spurs and find that reducing the phase discrimination frequency will significantly improve the @ 40kHz spurs. In the original design, other parameters will not be changed. Reduce the phase discrimination frequency and the corresponding fractional denominator to ensure that the numerator is 1 It still outputs 1966.12MHz signal. Table 2 is the test results.
Table 2 Spurious test results
Through the above test results, it is found that the integer boundary spurs have been significantly improved. Figure 3 is a redesigned optimized design based on the 3.84MHz phase discrimination frequency, with a loop bandwidth of 11.5kHz and a phase margin of 39 degrees.
Figure 3 Integer boundary spur optimization design 1
The performance test results of the output signal 1966.12MHz signal are shown in Table 3.
Table 3 Performance results of optimized design 1
In order to meet the 10dB spurious optimization goal, the parameters shown in Figure 4 were redesigned again, with a loop bandwidth of 8 kHz and a phase margin of 43 degrees.
Figure 4 Integer boundary spur optimization design 2
The performance test results are shown in Table 4.
Table 4 Performance results of optimized design 2
1. Summary
This article uses the LMX2531LQ2080E as an example to provide a method for optimizing the worst integer boundary spurs in fractional fractions, rather than using frequency avoidance. At the cost of 0.26 degrees of phase noise degradation, an integer boundary spur performance improvement of up to 10 dB is obtained. Of course, methods such as reducing the charge pump current and reducing the loop bandwidth will also properly improve the integer boundary spurs, but through experimental verification, it has been found that the degree of improvement in reducing the charge pump current is very limited, and the small charge pump current will also contribute to phase noise. Performance has a greater impact; too narrow loop bandwidth will bring a longer loop lock time, which has a limiting effect on the application of phase-locked loop technology. So if the phase noise performance requirements are not extremely harsh, you can try a smaller phase discrimination frequency to get a good spurious performance.
2. Reference materials
1. LMX2531 datasheet
2. LMX2531LQ2080E EvaluaTIon Board OperaTIng InstrucTIons
3. AN-1879 Fractional N frequency synthesis, Dean Banerjee
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