Hardware circuit of PHY device with Ethernet interface

The configuration process of DP83848I by LPC23xx is as follows:

① Send a reset signal with a pulse width greater than 1 μs, waiting for the completion of the auto-negotiation process;
â‘¡ Query the fifth bit of the basic mode status register (BMSR). When this bit goes high, it indicates that the auto-negotiation process is complete and the wait is over;
â‘¢ Query the 15, 14, 13, 12, and 11 bits of the BMSR to obtain the working mode of the Ethernet interface;
â‘£ Configure the working mode of LPC23xx Ethernet controller.


Figure 3 The hardware circuit of the PHY device of the Ethernet interface


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