1 Introduction
LED display has the advantages of high brightness, low failure, low energy consumption, long service life, diverse display content and rich display modes. It can be widely used in public places such as roads, finance, securities, stations, docks, stadiums, etc. The data usually comes from the host PC, which requires a high-speed channel to transfer a large amount of display data. The USB2.0 interface is undoubtedly a good solution. USB is powered by the bus, and has CRC error detection and error correction capability for real-time hot swapping, and supports multiple peripherals connected to the same connector, thus alleviating PC system resource conflicts. The advantages are that USB1. x is widely used on PC external devices. USB2.0 transmission speed is up to 480Mb/s, which is 40 times that of USB1.x and backward compatible with USB1.x. This allows a fast and large amount of data transfer to be achieved.
2, CY7C68013 Brief
CY7C68013 with high-speed Slave FIFO universal external interface is USBPRESS's USB2.0 integrated micro-processing chip, integrated with on-chip USB transceiver (SIE), enhanced 8051 microcontroller (the instruction system is fully compatible with ordinary 8051 microcontroller) and 8k program The memory area has 4 “large†endpoints (2 IN endpoints and 2 OUT endpoints) supporting USB 2.0 transmission and 4kB of on-chip RAM. The RAM can be configured as FIFOs with 4 “large†endpoints, 2 of which The "large" endpoints can be configured as dual, triple, and quad buffers (FIFOs), and one "large" endpoint can be configured for up to 2kB FIFOs. More importantly, the chip provides two for high-speed USB 2.0 transmission. Programmable external device interface and Slave FIFO and GPIF. These two general-purpose external interfaces can realize high-speed transmission of USB2.0 by coordinating with four "big" endpoints. This article only discusses the application of Slave FIFO programmable external device interface. .
The CY7C68013 is available in 56pin, 100pin, and 128pin packages. 56pin has all USB2.0 functions, while 100pin adds more I/O and more GPIF mode control signals to the 56pin. 128pin is based on 100pin. An address bus and a data bus for augmenting the data storage area are added. This application is based on the programmable external device interface Slave FIFO. A large amount of data transmission can be directly processed by the FPGA without expanding the external data storage area. The most economical 56pin CY7C68013 can be selected to meet the design requirements. The architecture is shown in Figure 1. .
Figure 1 Architecture of 56-pin CY7C68013
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