How to design an ESD protection circuit?

For most engineers, ESD is a challenge not only to protect expensive electronic components from being damaged by ESD, but also to ensure that the system continues to operate in the event of an ESD event. This requires an in-depth understanding of what happens when the ESD strikes, in order to design the correct ESD protection circuit.

Our hands have had an electrostatic discharge (ESD) experience, and even if you just walk past the carpet and touch some metal parts, it will instantly release the accumulated static electricity. Many of us have complained about the use of conductive blankets, ESD electrostatic wristbands and other requirements in the laboratory to meet industrial ESD standards. Many of us have used expensive unprotected circuits to damage expensive electronic components.

ESD is a challenge for some people because it does not require any damage when handling and assembling unprotected electronic components. This is a circuit design challenge because it is necessary to ensure that the system withstands the impact of ESD and then still works properly. It is better that no user-perceived faults occur after an ESD event.

Contrary to common sense, designers can completely prevent a system from failing after an ESD event and still continue to operate. Keep this in mind, let's take a closer look at what's going on in the ESD shock, and then show you how to design the right system architecture to handle ESD.

Simple ESD model

Charge a capacitor to a high voltage (typically 2kV to 8kV) and then release the charge through a closed switch into a "damaged" device ready to withstand ESD strikes (Figure 1). The polarity of the charge can be positive or negative, so both positive and negative ESD must be handled simultaneously.

Figure 1: Board-level ESD typically involves machine models (MM) and human body models (HBM)

The high transient voltage that destroys the damaged circuit typically has a rise time of a few nanoseconds and a discharge time of about 100 nanoseconds. Unlike damaged circuits, the sensitivity to positive and negative shocks can vary greatly, so you need to handle positive and negative shocks at the same time. The difference between the two most common models of human body model (HMB) and machine model (MM) is mainly in series resistance. The conductivity of the mannequin is not as good as that of metal.

The best protection against overvoltage damage is to limit or clamp with a non-linear circuit (Figure 2). The most common are specialized diodes that have very low impedance when they are forward biased or in the Zener breakdown region. The introduction of a voltage limiter can quickly cause some other event because a large surge current flows through the voltage limiter through the capacitor discharge.

Figure 2: The basic voltage limiting circuit prevents overvoltage damage.

Although high transient voltages are eliminated, replacing them with a few amps of inrush current can cause other problems in the system. Depending on the total impedance of the subsequent path, the inrush current can reach several amps. When designing I/O cells for a chip, it is common to see 4A to 16A of inrush current entering the device. Dealing with such huge transient surge currents has become a big problem in ESD design. Limiting the voltage is fairly easy, but the resulting current can reverse the circuitry and ground elsewhere in the system.

The current forced into the ground by the voltage limiter will cause an inductive ringing in that node of the system (Figure 3). The power supply typically travels along the ground and is a function of the power supply decoupling capacitance, so the system core still functions. However, the control lines connected to the board may be confusing because they are built relative to the ground outside the board. As a result, an ESD event can occur at a location and cause an input on the board to appear to be faulty.

Figure 3: Injecting a large inrush current into the ground through a voltage limiter will cause a rebound in the PCB ground and behave as a function of the connected inductance.

Fortress ESD protection

With board-level ESD, you can try to build a fortress and build multiple controlled access points on the Moat. The parts connected to the "City Wall" can be broadly divided into several categories: protocol controlled data, low bandwidth detection and control lines, and high speed interfaces. The first two are easier to handle, and the third is somewhat challenging. There are several different ways to protect these three parts from ESD damage.

Regardless of the end product, some form of protective enclosure will be part of the equipment. The circuit inside the isolation enclosure is the first line of defense that needs careful consideration. Ideally, metal enclosures that connect circuit boards can often be used, but modern products often use non-conductive plastics or other modern materials.

Circuit designers often have no control over the materials used to build the walls, but they have an unshirkable responsibility for protecting the fortress. Care must be taken when designing the enclosure that ESDs that reach any part of the exterior of the enclosure will have numerous paths into the internal circuitry.

Building a fortress that can self-prevent ESD strikes can start with a low-impedance grounding method. Establishing a ground and normal power integrity allows the printed circuit board (PCB) to maintain signal integrity throughout the board, even when subjected to large ground surge currents.

As a design engineer, you will ask everyone to fasten their seat belts so that they can handle a small amount of airflow. The airplane may swing up and down quickly, but if everyone has fastened the seat belt, everyone will be fixed and the aircraft will continue to fly. After that, you need to protect the external connections and limit the ESD event effects.

The protection circuit should be located at the board entry point, not downstream of the entry point. What may need to be addressed is the kilovolt potential caused by the arcing problem, or a few amps of surge current that is preferably processed at the edge of the board.

ESD protection for TVS voltage limiters

A transient voltage suppression (TVS) limiting diode can be used as a voltage limiter. They are divided into normal voltage, logic level and supply voltage. Common voltage types are: 12V, 5V, 3.3V, 2.5V, 1.8V, and 1.2V.

This number should look familiar because these devices are specifically designed for the needs of many CMOS devices. One specification is unlikely to meet all the requirements, they should be the right voltage to protect the device.

Modern CMOS processes significantly reduce the supply voltage to protect transistors with a lot of design margin and limited voltage range, which is worthy of our respect. These devices are typically fabricated using a foundry process that provides high current devices with low impedance characteristics in a small package.

Placing a TVS voltage limiter on the input line protects the input from damaging damage from ESD (Figure 4). However, such a voltage limiter cannot handle the signal chaos that occurs during host processing, nor can it handle the reversal effect due to a large ground current surge.

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Figure 4: Simple voltage-limiting voltage provides overvoltage protection but can cause inrush current problems

The inrush current should be limited and the signal should remain relatively local stable. As mentioned earlier, the performance difference between HBM and MM is very large. In many cases, adding some series resistance before the TVS device helps limit current surges and reduces ground bounce. As with HBM, the end result is reduced system stress.

Usually the bandwidth limit itself will not solve the ESD problem. Low-pass filters also require 60dB to 150dB of attenuation for small ESDs to eliminate transient voltages, which is difficult for simple passive filters. The TVS voltage limiter pulls the signal down between the power rails.

A first order RC circuit can then be used to maintain signal integrity (Figure 4). The capacitor can also be stabilized relative to the local input voltage. This approach protects a large number of low-bandwidth inputs, including "set and forget" control lines, sensor inputs, and similar objects.

Although much of what we discuss is to protect the input ports of the PCB, the output port protection is similar. TVS voltage limiters and additional resistors are also suitable here. Limiting the voltage helps prevent semiconductor damage and protects other components with voltage limitations.

The series resistance also contributes to the stability of the ground. In addition, keeping the ESD surge current away from the I/O unit of the digital chip prevents ground bounce inside the chip, allowing the processor to maintain normal operation when the external voltage limiter absorbs the inrush current surge.

ESD protection inside the chip

The ESD protection features within the IC are somewhat compromised for a variety of reasons. Both silicon and metal are optimized for the core functions of the IC and are not suitable for high current operation. Specialized TVS devices use silicon optimized for high current circuits with higher performance than PN junctions in normal CMOS.

In addition, I/O units with high current ESD protection take up a considerable amount of space, driving up IC costs. Moreover, high-frequency pins on the IC usually have no way to attach a large-sized ESD protection circuit because it generates a capacitive load.

As a general rule of thumb, the degree of ESD protection inside the chip is only sufficient to complete the IC production and solder to the PCB, but lacks the robust protection performance usually required by the application environment. If the connection needs to leave the PCB, it is usually necessary to use an external device for further protection.

EDS protection for data communication ports

A properly designed communication port uses a robust protocol that includes the use of cyclic redundancy check (CRC) coding to test the integrity of the data. The Ethernet, USB and CAN buses have developed CRC encoding and are transmitted with the data. A properly designed receiver will check if the CRC code matches the transmitted data. If it does not match, it means that either the data or the CRC encoding has an error and a request to resend the data will be issued.

Since ESD events last less than 100 ns, the CRC check, verify, and resend processes typically process ESD in an invisible manner. End users generally never realize that the corrupted information has been corrected. There are no protective measures in the structure of some other protocols.

The I2C, Serial Peripheral Interface (SPI), and System Management Bus (SMBus) communication designs work on the PCB and cannot verify and correct data. If there is some data to leave the board, make sure you have a way to verify the validity of the data.

Most modern communication paths use differential mode, which uses some form of low voltage differential signaling (LVDS). Each LVDS connection needs to be protected by TVS like all other signals. Magnetic field isolation (commonly used in Ethernet) and common mode chokes help resolve common mode variations due to ground bounce in ESD events. Optical isolation or magnetic field isolation should be used when the input signal does not share the same ground as the PCB.

High-speed data streams that require sophisticated data integrity but do not include error checking are particularly difficult to prevent ESD strikes. Understanding how devices provide serial data rates above 1GB/s and complete communication protocol protection can avoid this problem.

ESD protection of analog signals and digital intelligence

Basic analog TVS protection is required for any analog signals that leave or enter the board. You need to consider the bandwidth of the connection channel to determine what other measures should be taken next. Most analog control signals, motion control systems, audio and indicator lights do not require more action because the response time of the devices used is longer. The RF front end is the physical layer of the communication channel and is self-correcting by an error detection mechanism that is part of the protocol.

The hardware can only provide so much protection. If a processor in the system center needs to complete monitoring and control, then some options are needed. The techniques presented here can make your processor no longer lost or need to go through a reset cycle. What happens under this host control is another matter that needs to be considered.

In general, you need to put some intelligence into the processor code so that it can identify the wrong information and handle it correctly. Slow detection and control line problems can be easily solved by time-division polling ports. Since the ESD event is very short, if the data on the port is stable for multiple samples in a few milliseconds, then there is no catastrophic event such as ESD.

In addition, the output can be refreshed as part of the rendering process. This step is not needed if the processor is a memory unit, but if the data is locked remotely, then a refresh routine is needed to manage the corrupt event.

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