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1 Introduction
In order to prevent traffic accidents in cars, when the car intelligent detection device detects danger in front, it must send a warning message to the driver. The voice alarm clearly indicates the danger to the driver so that the driver can take timely and accurate measures. Therefore, this paper proposes a digital voice processing technology, which first digitally collects and stores alarm information of various conditions. When it encounters danger, it will judge the danger type and automatically select and play the stored alarm information. Due to the large amount of voice information, direct storage requires a large storage space. For this reason, this paper uses FPGA to implement ADPCM (Adaptive Differential Pulse Code Modulation) codec design, which compresses and stores voice information. The amount of information stored has doubled.
2 system structure and principle
The system design is based on single chip and FPGA. The working state of the MCU control system, start recording and playback, and time and display the recording and playback time. The FPGA compresses, stores, and decompresses the collected data. The MCU works in coordination with the FPGA to improve the efficiency and stability of the system. The system structure is shown in Figure 1.
First, the various alarm sounds that are desired to be collected are converted into digital signals by the A/D converter through the forward channel (microphone, differential amplifier, filter, adder) and sent to the FPGA for ADPCM compression encoding processing, and then stored. Go to the static memory SRAM. When it is dangerous, the MCU judges the danger, controls the FPGA to take the corresponding voice data out of the SRAM and decode it, then sends it to the 8-bit D/A converter, converts it into an analog signal, and then passes the backward channel (filtering The alarm, the correction circuit, the power amplifier, and the speaker) reproduce the alarm sound.
3 system main hardware design
3.1 Preamplifier
The electret microphone is used to collect the voice signal and convert the signal whose amplitude is millivolt. When the system is processed by the front stage, the signal-to-noise ratio of the input of the amplifier should be increased as much as possible to ensure accurate and stable gain of the amplifier circuit. . To this end, this paper designs a detection amplification circuit as shown in Figure 2. The front stage of the circuit uses a voltage follower, which uses the input resistance to be infinite and the output tends to zero, providing high input resistance for impedance transformation and isolation. The latter stage uses a differential amplifier to obtain a higher common mode rejection ratio. Circuit immunity.
The voltage follower consists of the excellent low-noise audio amplifier NE5532 with an operating voltage of 12 V and a working bandwidth of 10 MHz, making it ideal for voice information processing. The differential amplifier is implemented with the AD620. The AD620 is actually a differential amplifier with low offset voltage and high common-mode rejection ratio, so it has excellent performance when dealing with weak signals, that is, amplification and noise cancellation. Its gain G=1+(49.4 kΩ/Rg) (Rg is a resistor connected between pins 1 and 8). Adjust potentiometer R1 so that the amplified signal amplitude is between -2.5 V and 2.5 V, which is convenient for A/D converter sample quantization.
3.2 Bandpass filter
The speech signal is easily picked up after being amplified, so the out-of-band clutter is filtered out by a bandpass filter before data acquisition. The human voice frequency ranges from 300 Hz to 3.4 kHz, so the passband range of the filter should be 300 Hz to 3.4 kHz. Such a wide frequency band must be implemented by cascading a low-pass part and a high-pass part.
High-pass filter design index: passband cutoff frequency fp=300Hz, passband allows maximum attenuation αp≤3 dB; to eliminate power frequency interference, determine the stopband cutoff frequency fs=50 Hz, and the stopband allows minimum attenuation as>40 dB. The two-stage second-order Butterworth high-pass filter is cascaded. The simulation results are shown in Figure 3.
The design specifications of the low-pass filter are: passband cutoff frequency fp=3 400 Hz, passband allows maximum attenuation αp≤3 dB; to suppress sampling aliasing distortion, determine the stopband cutoff frequency fs=4 000 Hz, stopband permission The minimum attenuation is ≥ 40 dB. This system design is suitable because the elliptical filter can achieve a narrower transition bandwidth than other filters. The filter-assisted design software Filter Wiz Pro is used to obtain the fifth-order elliptical low-pass filter circuit as shown in Fig. 4. The simulation results are shown in Fig. 5.
By cascading high-pass and low-pass filters, a 300 Hz to 3.4 kHz bandpass filter can be obtained. Experiments show that the filter works well and meets the design specifications. The design of the bandpass filter of the backward channel is the same.
4 system software design
4.1 FPGA section
The ADPCM encoder and decoder are implemented using Altera's Cyclone series EPlC6Q-240C8. The device contains 120 000 typical gate resources, 5 980 logic cells, 6 RAM blocks, 92 160 bit RAM or ROM, 2 digital PLLs, 185 programmable I/O ports, and a maximum operating clock of over 300 MHz. And in the system configuration through the JTAG interface.
ADPCM is a waveform coding technique that utilizes highly correlated samples and quantized order adaptive compression data between samples. ADPCM combines the adaptive characteristics of APCM with the differential characteristics of DPCM. Its core idea is to use adaptive to change the size of the quantization step, that is, to use a small quantization step to encode small differences, use a large quantization step to encode large differences; use past sample values ​​to estimate the next input sample. The predicted value, the difference between the actual sample value and the predicted value is always the smallest. The input signal of the ADPCM codec is G.711 PCM code. If the sampling frequency is 8 kHz, each code is 8 bits, its data rate is 64 Kb/s, and the output code of ADPCM is “adaptive quantizer. The output, which is a 4-bit differential signal, has a sampling frequency of 8 kHz and a data rate of 32 Kb/s, which results in a 2:1 data compression.
Encoding process: Calculating a difference d between the current sample value Sc of the 8-bit two's complement and the last predicted sample value Sp, the difference being quantized to output a 4-bit ADPCM code I. In the algorithm, a structure variable is defined to store the predicted sample value Sp and the quantization step size q, and two tables are defined: one table is an index adjustment table, and the input is a difference quantization code I for updating the step index; One table is a step adjustment table whose input is the step index and the output is the step size q. When encoding, first use the step index of the previous sample point to check the step size adjustment table to find the step size q, and then determine the 4-bit ADPCM code value I according to the following formula:
Then, the encoded value I is used as an input of the index adjustment table, and the table output index is adjusted and added to the original step index in the structure variable to generate a new step index, which is used in the encoding of the next sample value. After the encoder outputs I, it is necessary to repeat the calculation process exactly the same as the decoding to obtain a new predicted sample value Sp.
The decoding process: firstly, the step size is adjusted by the step index to obtain the quantization step size, and the difference quantization code I is inversely quantized to obtain the speech difference d, which is the inverse process of finding I; and then with the previous prediction value Sp. The current speech signal Sc is reconstructed together; finally, the predicted value Sp is updated with Sp=Sc, and the quantization step index is updated with I.
After the design is completed, the ADPCM codec is simulated, and the simulation results are shown in Fig. 6. AD_DataBus is the input signal before encoding and is generated by Testbench. When the code enable signal P1_7 is "0", encoding is started, and when P1_7 is changed to "1", the code is masked. At this time, the decoding enable signal P1_4 is "0", and decoding is started. When P1_4 is hopped to "1", the decoding is masked. It can be seen that the pre-encoding input signal AD_DataBus and the decoder output DA_DataBus basically meet the requirements. Since the ADPCM algorithm itself is lossy compression, it can be determined that the design of this part is correct and reliable.
4.2 MCU part
The single-chip microcomputer is the control center of the whole system. It is responsible for detecting the danger and judging its type to select and play the corresponding alarm information. The workflow is shown in Figure 7. This paper gives the use of 3 buttons to represent the occurrence of 3 kinds of dangers, for the detection of single-chip microcomputer.
Select the commonly used 51 series single-chip AT89C52, use C51 language programming to complete the program design, the experimental results are ideal.
5 Conclusion
The design of this system is to use the single chip and the FPGA to give full play to their respective advantages. Obtaining the desired effect, it has strong practicability, and it also proves the efficiency of using the programmable logic device to realize the speech digital compression processing. Experiments show that the system can reproduce the recorded alarm voice well and has high fidelity. The driver can change the alarm sound at will according to his or her own preferences. In critical situations, the system will automatically issue clear alarm prompts, greatly improving the safety of driving.
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